13.6.31 PWM Generator x Duty Cycle Adjustment Register
| Name: | PGxDCA |
| Offset: | 0x350, 0x386, 0x3BC, 0x3F2, 0x45E, 0x4CA |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PGxDCA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – PGxDCA[7:0] PWM Generator x Duty Cycle Adjustment Value bits
Depending on the state of the selected PCI source, the PGxDCA value will be
added to the value in the PGxDC register to create the effective duty cycle. When the
PCI source is active, PGxDCA is added. When the PCI source is inactive, no adjustment
is made. Duty cycle adjustment is disabled when PGxDCA[7:0] = 0. The
PCI source is selected using the DTCMPSEL bit.