13.6.1 PWM Clock Control Register

Note:

A device-specific unlock sequence must be performed before this bit can be cleared.
Changing the MCLKSEL[1:0] bits while ON (PGxCONL[15]) = 1 is not recommended.

Name:	PCLKCON
Offset:	0x300


Bit	15	14	13	12	11	10	9	8
	HRRDY	HRERR						LOCK
Access	R/W	R/W						R/W
Reset	0	0						0


Bit	7	6	5	4	3	2	1	0
			DIVSEL[1:0]				MCLKSEL[1:0]
Access			R/W	R/W			R/W	R/W
Reset			0	0			0	0

Bit 15 – HRRDY High-Resolution Ready bit

Value	Description
`1`	The high-resolution circuitry is ready
`0`	The high-resolution circuitry is not ready

Bit 14 – HRERR High-Resolution Error bit

Value	Description
`1`	An error has occurred; PWM signals will have limited resolution
`0`	No error has occurred; PWM signals will have full resolution when HRRDY = `1`

Bit 8 – LOCK Lock bit⁽¹⁾

Value	Description
`1`	Write-protected registers and bits are locked
`0`	Write-protected registers and bits are unlocked

Bits 5:4 – DIVSEL[1:0] PWM Clock Divider Selection bits

Value	Description
`11`	Divide ratio is 1:16
`10`	Divide ratio is 1:8
`01`	Divide ratio is 1:4
`00`	Divide ratio is 1:2

Bits 1:0 – MCLKSEL[1:0] PWM Master Clock Selection bits⁽²⁾

Value	Description
`11`	AF_PLLO – Auxiliary PLL post-divider output
`10`	F_PLLO – Primary PLL post-divider output
`01`	AF_VCO/2 – Auxiliary VCO/2
`00`	F_OSC

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