13.6.21 PWM Generator x PCI Register Low
| Name: | PGxCLPCIL |
| Offset: | 0x33C, 0x372, 0x3A8, 0x3DE, 0x44A, 0x4B6 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSYNCDIS | TERM[2:0] | AQPS | AQSS[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWTERM | PSYNC | PPS | PSS[4:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – TSYNCDIS Termination Synchronization Disable bit
| Value | Description |
|---|---|
1 |
Termination of latched PCI occurs immediately |
0 |
Termination of latched PCI occurs at PWM EOC |
Bits 14:12 – TERM[2:0] Termination Event Selection bits
| Value | Description |
|---|---|
111 |
Selects PCI Source #9 |
110 |
Selects PCI Source #8 |
101 |
Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits) |
100 |
PGxTRIGC trigger event |
011 |
PGxTRIGB trigger event |
010 |
PGxTRIGA trigger event |
001 |
Auto-Terminate: Terminates when PCI source transitions from active to inactive |
000 |
Manual Terminate: Terminates on a write of ‘ |
Bit 11 – AQPS Acceptance Qualifier Polarity Select bit
| Value | Description |
|---|---|
1 |
Inverted |
0 |
Not inverted |
Bits 10:8 – AQSS[2:0] Acceptance Qualifier Source Selection bits
| Value | Description |
|---|---|
111 |
SWPCI control bit only (qualifier forced to ‘ |
110 |
Selects PCI Source #9 |
101 |
Selects PCI Source #8 |
100 |
Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits) |
011 |
PWM Generator is triggered |
010 |
LEB is active |
001 |
Duty cycle is active (base PWM Generator signal) |
000 |
No acceptance qualifier is used (qualifier forced to ‘ |
Bit 7 – SWTERM PCI Software Termination bit
A write of ‘1’ to this location will produce a termination
event. This bit location always reads as ‘0’.
Bit 6 – PSYNC PCI Synchronization Control bit
| Value | Description |
|---|---|
1 |
PCI source is synchronized to PWM EOC |
0 |
PCI source is not synchronized to PWM EOC |
Bit 5 – PPS PCI Polarity Select bit
| Value | Description |
|---|---|
1 |
Inverted |
0 |
Not inverted |
Bits 4:0 – PSS[4:0] PCI Source Selection bits
| Value | Description |
|---|---|
11111 |
CLC1 |
11110 |
Reserved |
| 11101 | Comparator 3 output |
| 11100 | Comparator 2 output |
11011 |
Comparator 1 output |
11010 |
PWM Event D |
11001 |
PWM Event C |
11000 |
PWM Event B |
10111 |
PWM Event A |
| 10110 | Device pin, PCI[22] |
| 10101 | Device pin, PCI[21] |
| 10100 | Device pin, PCI[20] |
| 10011 | Device pin, PCI[19] |
10010 |
RPn input, PCI18R |
10001 |
RPn input, PCI17R |
10000 |
RPn input, PCI16R |
01111 |
RPn input, PCI15R |
01110 |
RPn input, PCI14R |
01101 |
RPn input, PCI13R |
01100 |
RPn input, PCI12R |
01011 |
RPn input, PCI11R |
01010 |
RPn input, PCI10R |
01001 |
RPn input, PCI9R |
01000 |
RPn input, PCI8R |
00111 |
Reserved |
00110 |
Reserved |
00101 |
Reserved |
00100 |
Reserved |
00011 |
Internally connected to Combo Trigger B |
00010 |
Internally connected to Combo Trigger A |
00001 |
Internally connected to the output of PWMPCI[2:0] MUX |
00000 |
Tied to ‘ |