13.6.10 PWM Event Output Control Register y

Note:
  1. The event signal is stretched using the peripheral clock because different PGs may be operating from different clock sources. The leading edge of the event pulse is produced in the clock domain of the PWM Generator. The trailing edge of the stretched event pulse is produced in the peripheral clock domain.
  2. No event will be produced if the selected PWM Generator is not present.
  3. This is the PWM Generator output signal prior to Output mode logic and any output override logic.
  4. This signal should be the PGx_clk domain signal prior to any synchronization into the system clock domain.
  5. ‘y’ denotes a common instance (A-F).
Name: PWMEVTy(2,5)
Offset: 0x031E, 0x0320, 0x0322, 0x0324, 0x0326, 0x0328

Bit 15141312111098 
 EVTyOENEVTyPOLEVTySTRDEVTySYNC     
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 EVTySEL[3:0] EVTyPGS[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 15 – EVTyOEN PWM Event Output Enable bit

ValueDescription
1

Event output signal is output on PWMEVTy pin
0

Event output signal is internal only

Bit 14 – EVTyPOL PWM Event Output Polarity bit

ValueDescription
1

Event output signal is active-low
0

Event output signal is active-high

Bit 13 – EVTySTRD PWM Event Output Stretch Disable bit

ValueDescription
1

Event output signal pulse width is not stretched
0

Event output signal is stretched to eight PWM clock cycles minimum(1)

Bit 12 – EVTySYNC PWM Event Output Sync bit

Event output signal pulse will be two system clocks when this bit is set and EVTySTRD = 1.

ValueDescription
1 Event output signal is synchronized to the system clock
0 Event output is not synchronized to the system clock

Bits 7:4 – EVTySEL[3:0] PWM Event Selection bits

ValueDescription
1111

High-resolution error event signal
1110-1010

Reserved
1001

ADC Trigger 2 signal
1000

ADC Trigger 1 signal
0111

STEER signal (available in Push-Pull Output modes only)(4)
0110

CAHALF signal (available in Center-Aligned modes only)(4)
0101

PCI Fault active output signal
0100

PCI current-limit active output signal
0011

PCI feed-forward active output signal
0010

PCI Sync active output signal
0001

PWM Generator output signal(3)
0000

Source is selected by the PGTRGSEL[2:0] bits

Bits 2:0 – EVTyPGS[2:0]  Combinatorial PWM Logic Destination Selection bits

ValueDescription
111

Logic function is assigned to the PWM8H or PWM8L pin
110 Reserved
101

Logic function is assigned to the PWM6H or PWM6L pin
100 Reserved
011

Logic function is assigned to the PWM4H or PWM4L pin
010

Logic function is assigned to the PWM3H or PWM3L pin
001

Logic function is assigned to the PWM2H or PWM2L pin
000

No assignment, combinatorial PWM logic function is disabled