13.6.27 PWM Generator x Leading-Edge Blanking Register Low
Note:
- Bits[2:0] are read-only and always
remain as ‘
0’.
| Name: | PGxLEBL |
| Offset: | 0x348, 0x37E, 0x3B4, 0x3EA, 0x456, 0x4C2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LEB[15:8] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LEB[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – LEB[15:0] Leading-Edge Blanking Period bits(1)
Leading-Edge Blanking period. The three LSbs of the blanking time are not used,
providing a blanking resolution of eight PGx_clks. The minimum blanking period is
eight PGx_clks which occurs when LEB[15:3] = 0.