13.3.38 ADC Control Register 5 Low
Legend: HSC = Hardware Settable/Clearable bit
| Name: | ADCON5L |
| Offset: | 0xC00 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SHRRDY | |||||||||
| Access | R/HSC | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SHRPWR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 15 – SHRRDY Shared ADC Core Ready Flag bit
| Value | Description |
|---|---|
1 |
ADC core is powered and ready for operation. |
0 |
ADC core is not ready for operation. |
Bit 7 – SHRPWR Shared ADC Core Power Enable bit
| Value | Description |
|---|---|
1 |
ADC core is powered. |
0 |
ADC core is off. |