13.3.19 ADC Digital Filter x Control Register (x = 0, 1, 2, 3)

Bit 15 – FLEN Filter Enable bit

Value	Description
`1`	Filter is enabled.
`0`	Filter is disabled and the RDY bit is cleared.

If MODE[1:0] = 00:

111 = 128x (16-bit result in the ADFLxDAT register is in 12.4 format)

110 = 32x (15-bit result in the ADFLxDAT register is in 12.3 format)

101 = 8x (14-bit result in the ADFLxDAT register is in 12.2 format)

100 = 2x (13-bit result in the ADFLxDAT register is in 12.1 format)

011 = 256x (16-bit result in the ADFLxDAT register is in 12.4 format)

010 = 64x (15-bit result in the ADFLxDAT register is in 12.3 format)

001 = 16x (14-bit result in the ADFLxDAT register is in 12.2 format)

000 = 4x (13-bit result in the ADFLxDAT register is in 12.1 format)

If MODE[1:0] = 11 (12-bit result in the ADFLxDAT register in all instances):

111 = 256x

110 = 128x

101 = 64x

100 = 32x

011 = 16x

010 = 8x

001 = 4x

000 = 2x

Value	Description
`1`	Common ADC interrupt will be generated when the filter result will be ready.
`0`	Common ADC interrupt will not be generated for the filter.

This bit is cleared by hardware when the result is read from the ADFLxDAT register.

Value	Description
`1`	Data in the ADFLxDAT register are ready.
`0`	The ADFLxDAT register has been read and new data in the ADFLxDAT register are not ready.

Name:	ADFLxCON
Offset:	0xB6A, 0xB6E, 0xB72, 0xB76