13.3.30 ADC Channel Trigger 5 Selection Registers Low

Name:	ADTRIG5L
Offset:	0xB94


Bit	15	14	13	12	11	10	9	8
				TRGSRC21[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				TRGSRC20[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 12:8 – TRGSRC21[4:0] Trigger Source Selection for Corresponding Analog Inputs bits

Value	Description
`11111`	ADTRG31 (PPS input)
`11110`	PTG
`11101`	CLC2
`11100`	CLC1
`11011-11000`	Reserved
`10111`	SCCP4 output compare trigger
`10110`	SCCP3 output compare trigger
`10101`	SCCP2 output compare trigger
`10100`	SCCP1 output compare trigger
`10011`	Reserved
`10010`	CLC4
`10001`	CLC3
`10000`	Reserved
`01111`	SCCP4 trigger
`01110`	SCCP3 trigger
`01101`	SCCP2 trigger
`01100`	SCCP1 trigger
`01011`	PWM4 Trigger 2
`01010`	PWM4 Trigger 1
`01001`	PWM3 Trigger 2
`01000`	PWM3 Trigger 1
`00111`	PWM2 Trigger 2
`00110`	PWM2 Trigger 1
`00101`	PWM1 Trigger 2
`00100`	PWM1 Trigger 1
`00011`	Reserved
`00010`	Level software trigger
`00001`	Common software trigger
`00000`	No trigger is enabled

Bits 4:0 – TRGSRC20[4:0] Common Interrupt Enable for Corresponding Analog Inputs bits

Value	Description
`11111`	ADTRG31 (PPS input)
`11110`	PTG
`11101`	CLC2
`11100`	CLC1
`11011-11000`	Reserved
`10111`	SCCP4 output compare trigger
`10110`	SCCP3 output compare trigger
`10101`	SCCP2 output compare trigger
`10100`	SCCP1 output compare trigger
`10011`	Reserved
`10010`	CLC4
`10001`	CLC3
`10000`	Reserved
`01111`	SCCP4 trigger
`01110`	SCCP3 trigger
`01101`	SCCP2 trigger
`01100`	SCCP1 trigger
`01011`	PWM4 Trigger 2
`01010`	PWM4 Trigger 1
`01001`	PWM3 Trigger 2
`01000`	PWM3 Trigger 1
`00111`	PWM2 Trigger 2
`00110`	PWM2 Trigger 1
`00101`	PWM1 Trigger 2
`00100`	PWM1 Trigger 1
`00011`	Reserved
`00010`	Level software trigger
`00001`	Common software trigger
`00000`	No trigger is enabled

DS70005633B

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