13.3.11 ADC Interrupt Enable Register High
Note:
- Bit availability depends on the number of supported ADC channels. Refer to dsPIC33CK256MC006 Product Families for ADC channel availability on package variants.
| Name: | ADIEH(1) |
| Offset: | 0xB22 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IE[21:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:0 – IE[21:16] Common Interrupt Enable bits
| Value | Description |
|---|---|
1 |
Common and individual interrupts are enabled for the corresponding channel. |
0 |
Common and individual interrupts are disabled for the corresponding channel. |