13.3.33 ADC Level-Sensitive Trigger Control Register High
| Name: | ADLVLTRGH |
| Offset: | 0xBD2 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LVLEN[21:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:0 – LVLEN[21:16] Level Trigger for Corresponding Analog Input Enable bits
| Value | Description |
|---|---|
1 |
Input trigger is level-sensitive. |
0 |
Input trigger is edge-sensitive. |