13.3.13 ADC Data Ready Status Register High

Note:
  1. Bit availability is dependent on the number of supported ADC channels. Refer to dsPIC33CK256MC006 Product Families for ADC channel availability on package variants.

Legend: HSC = Hardware Settable/Clearable bit

Name: ADSTATH(1)
Offset: 0xB32

Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   AN[21:16]RDY 
Access HSC/RHSC/RHSC/RHSC/RHSC/RHSC/R 
Reset 000000 

Bits 5:0 – AN[21:16]RDY Common Interrupt Enable for Corresponding Analog Input bits

ValueDescription
1

Channel conversion result is ready in the corresponding ADCBUFx register.
0

Channel conversion result is not ready.