13.3.6 ADC Control Register 3 High

Note:

The ADC input clock frequency, selected by the CLKSEL[1:0] bits, must not exceed parameters AD9, AD10 and AD11 in Table 30-31.
The ADC clock frequency, after the first divider selected by the CLKDIV[5:0] bits, must not exceed parameters AD9, AD10 and AD11 in Table 30-31.

Name:	ADCON3H
Offset:	0xB0A


Bit	15	14	13	12	11	10	9	8
	CLKSEL[1:0]		CLKDIV[5:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SHREN
Access	R/W
Reset	0

Bits 15:14 – CLKSEL[1:0] ADC Module Clock Source Selection bits⁽¹⁾

Value	Description
`11`	F_VCO/4
`10`	F_VCO/3
`01`	F_OSC
`00`	F_P

Bits 13:8 – CLKDIV[5:0] ADC Module Clock Source Divider bits⁽²⁾

The divider forms a T_CORESRC clock used by the ADC core from the T_SRC ADC module clock source, selected by the CLKSEL[1:0] bits. Then, each ADC core individually divides the T_CORESRC clock to get a core-specific T_ADCORE clock using the ADCS[6:0] bits in the ADCORExH register or the SHRADCS[6:0] bits in the ADCON2L register.

Value	Description
`111111`	64 Source Clock Periods
. . .
`000011`	4 Source Clock Periods
`000010`	3 Source Clock Periods
`000001`	2 Source Clock Periods
`000000`	1 Source Clock Period

Bit 7 – SHREN Shared ADC Core Enable bit

Value	Description
`1`	Shared ADC core is enabled.
`0`	Shared ADC core is disabled.

DS70005633B

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