17.2.1.9 List x Status Register

Note:
  1. Software can clear or set this bit without affecting the conversion; however, setting this bit will generate the list interrupt if enabled.
  2. When TRGEN bit = '1' in ITCSLxCON register, the NEXT[5:0] bits are locked from user writes.
Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown
Name: ITCLSxSTAT
Offset: 0x3A0, 0x3BC, 0x3D8

Bit 3130292827262524 
 TACTBUSY       
Access HSHS 
Reset 00 
Bit 2322212019181716 
   INT      
Access HS 
Reset 0 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   NEXT[5:0] 
Access HS HC R/WXXX 
Reset 000000 

Bit 31 – TACT Trigger Active bit

ValueDescription
1

The trigger is asserted.
0

The trigger is not asserted.

Bit 30 – BUSY Busy Flag bit

ValueDescription
1

The ITC is busy.
0

The ITC is idle.

Bit 21 – INT  List Interrupt Flag bit(1)

ValueDescription
1

List interrupt was generated.
0

The interrupt was not generated.

Bits 5:0 – NEXT[5:0]  Entry to Convert on Next Trigger bits(2)

Indicates the next entry number on the list that will be converted for the trigger.
ValueDescription
63-32

Reserved
31

Record 31 next
...
1

Record 1 next
0

Record 0 next