17.2.1.20 Acquisition Sequence
Commands Array Map Register
Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | SDATAMAP |
| Offset: | 0x7C3080 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | DATASEQ3[2:0] | Reserved | SPLIT3[1:0] | |
| Access | | | R/W | R/W | R/W | r | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | DATASEQ2[2:0] | Reserved | SPLIT2[1:0] | |
| Access | | | R/W | R/W | R/W | r | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | DATASEQ1[2:0] | Reserved | SPLIT1[1:0] | |
| Access | | | R/W | R/W | R/W | r | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | DATASEQ0[2:0] | Reserved | SPLIT0[1:0] | |
| Access | | | R/W | R/W | R/W | r | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 29:27 – DATASEQ3[2:0] Acquisition Sequence Number Bits for Commands
from SnDATACMD12 to SnDATACMD15
These bits must
match DATASEQ[2:0] bits settings in the ITCSLxSEQ register.
Bit 26 – Reserved
Bits 25:24 – SPLIT3[1:0] Several Sequences
Split Bits for Commands from SnDATACMD12 to SnDATACMD15
Bits 21:19 – DATASEQ2[2:0] Acquisition Sequence Number Bits for Commands from SnDATACMD8 to
SnDATACMD11
These bits must match
DATASEQ[2:0] bits settings in ITCSLxSEQ register.
Bit 18 – Reserved
Bits 17:16 – SPLIT2[1:0] Several Sequences
Split Bits for Commands from SnDATACMD8 to SnDATACMD11
Bits 13:11 – DATASEQ1[2:0] Acquisition Sequence Number Bits for Commands from SnDATACMD4 to
SnDATACMD7
These bits must match
DATASEQ[2:0] bits settings in the ITCSLxSEQ register.
Bit 10 – Reserved
Bits 9:8 – SPLIT1[1:0] Several Sequences
Split Bits for Commands from SnDATACMD4 to SnDATACMD7
Bits 5:3 – DATASEQ0[2:0] Acquisition Sequence Number Bits for Commands from SnDATACMD0 to
SnDATACMD3
These bits must match
DATASEQ[2:0] bits settings in the ITCSLxSEQ register.
Bit 2 – Reserved
Bits 1:0 – SPLIT0[1:0] Several Sequences
Split Bits for Commands from SnDATACMD0 to SnDATACMD3
