17.2.1.13 List x Acquisition and Post-Processing Control Register
Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | ITCLSxSEQ |
| Offset: | 0x3B0, 0x3CC, 0x3E8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CVDCAP[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DATASEQ[2:0] | MATHSEQ[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ACCEN | ACCCNT[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 0 | ||||
Bits 30:28 – CVDCAP[2:0] CVD Internal Capacitance Selection bits
| Value | Description |
|---|---|
| 7 | 20 pF |
| ... | |
| 2 | 7.5 |
| 1 | 5 |
| 0 | 2.5 |
Bits 23:21 – DATASEQ[2:0] Acquisition Commands Sequence Select bits
| Value | Description |
|---|---|
7-4 |
Software defined acquisition sequences. |
| ... | |
3 |
Reserved |
2 |
Hardware CVD acquisition sequence |
1 |
Reserved |
0 |
Default acquisition sequence when the record’s analog input is sampled during time defined by SAMC[4:0] bits and then converted. |
Bits 19:17 – MATHSEQ[2:0] Post-Processing Commands Sequence Select bits
| Value | Description |
|---|---|
7-4 |
Application defined post-processing sequences. |
| ... | |
1 |
Default CVD post-processing sequence. |
0 |
Default post-processing sequence when the result of conversion is written into the record’s result register ITCRESx. |
Bit 7 – ACCEN Accumulation Enable bit
'1'Bits 3:0 – ACCCNT[3:0] Number of Record Accumulations Selection bits
| Value | Description |
|---|---|
15-1 |
Each record in the list is executed 2ACCCNT[3:0] times. |
0 |
Each record in the list is executed one time. |