17.2.1.12 List x Multiple Connections Selection Register

Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown

Name:	ITCLSxMUL
Offset:	0x3AC, 0x3C8, 0x3E4


Bit	31	30	29	28	27	26	25	24
	MUL31	MUL30	MUL29	MUL28	MUL27	MUL26	MUL25	MUL24
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	MUL23	MUL22	MUL21	MUL20	MUL19	MUL18	MUL17	MUL16
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MUL15	MUL14	MUL13	MUL12	MUL11	MUL10	MUL9	MUL8
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MUL7	MUL6	MUL5	MUL4	MUL3	MUL2	MUL1	MUL0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – MUL Pins from CVDAN0 to CVDAN31 Selection to Connected Together bits