17.2.1.18 Acquisition Sequence Commands Word x Register
Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | SDATACMDx |
| Offset: | 0x7C3000, 0x7C3004, 0x7C3008, 0x7C300C, 0x7C3010, 0x7C3014, 0x7C3018, 0x7C301C, 0x7C3020, 0x7C3024, 0x7C3028, 0x7C302C, 0x7C3030, 0x7C3034, 0x7C3038, 0x7C303C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| END | LOOP[3:0] | DMASTP | Reserved[2:1] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | r | r | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Reserved[0] | MSTART | SECOND | |||||||
| Access | r | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DISCHRG | CHRG | CONV | BAL | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PCC[1:0] | PCB[1:0] | PCA[1:0] | PC0[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – END Last Command in Sequence bit
| Value | Description |
|---|---|
1 |
This command is last in the sequence. |
0 |
There is the next command after this command. |
Bits 30:27 – LOOP[3:0] Wait bits
| Value | Description |
|---|---|
12-15 |
Reserved |
| 11 | The command waits for the new command that has been sent by DMA to SDATACMDx register. |
| 10 | The command waits for Timer D with delay defined by TMRD[7:0] bits in ITCLSxTMR register. |
| 9 | The command waits for Timer C with delay defined by TMRC[7:0] bits in ITCLSxTMR register. |
| 5-8 |
Reserved |
| 4 | The command waits for ADC’s end of conversion. |
| 3 | The command waits for delay defined in SAMC[4:0] bits in ITCLSxCON register. |
2 |
The command waits for Timer B with delay defined by TMRB[7:0] bits in ITCLSxTMR register. |
1 |
The command waits for Timer A with delay defined by TMRA[7:0] bits in ITCLSxTMR register. |
0 |
No delay, the next instruction must be executed right away. |
Bit 26 – DMASTP DMA Transfer of New Command Trigger bit
| Value | Description |
|---|---|
1 |
This command requests the DMA to transfer new commands in SDATACMDx registers. |
0 |
DMA is not requested. |
Bits 25:23 – Reserved[2:0]
Bit 22 – MSTART Post-Processing Math Sequence Start bit
| Value | Description |
|---|---|
1 |
This command executes the math sequence, |
0 |
The math sequence is not executed, |
Bit 18 – SECOND Second Post-Processing Math Sequence Start bit
| Value | Description |
|---|---|
1 |
The second math sequence is executed. |
0 |
The first math sequence is executed. |
Bit 15 – DISCHRG CVD Capacitors Array Discharge bit
| Value | Description |
|---|---|
1 |
The command with connect the CVD capacitors array to VSS (ground). |
0 |
The discharge switch is open. |
Bit 14 – CHRG CVD Capacitors Array Charge bit
| Value | Description |
|---|---|
1 |
The command with connect the CVD capacitors array to VDD (power). |
0 |
The charge switch is open. |
Bit 13 – CONV ADC5 Conversion Request bit
| Value | Description |
|---|---|
1 |
The command will start a conversion of CVD capacitors array level. |
0 |
The conversion is not requested. |
Bit 12 – BAL Balance Charge bit
| Value | Description |
|---|---|
1 |
The command will connect the CVD capacitors array to sensor CVDANx pin. |
0 |
The balance switch is open. |
Bits 7:6 – PCC[1:0] ITCTXC Register Level bits
| Value | Description |
|---|---|
3 |
CVDTXx pins defined in ITCTXC register are tri-stated. |
2 |
CVDTXx pins defined in ITCTXC register are set to a high level. |
1 |
CVDTXx pins defined in ITCTXC register are set to a low level. |
0 |
ITCTXC register is not used, the pins defined in ITCTXC are controlled by TRIS and LAT registers. |
Bits 5:4 – PCB[1:0] ITCTXB Register Level bits
| Value | Description |
|---|---|
3 |
CVDTXx pins defined in ITCTXB register are tri-stated. |
2 |
CVDTXx pins defined in ITCTXB register are set to a high level. |
1 |
CVDTXx pins defined in ITCTXB register are set to a low level. |
0 |
ITCTXB register is not used, the pins defined in ITCTXB are controlled by TRIS and LAT registers. |
Bits 3:2 – PCA[1:0] ITCTXA Register Level bits
| Value | Description |
|---|---|
3 |
CVDTXx pins defined in ITCTXA register are tri-stated. |
2 |
CVDTXx pins defined in ITCTXA register are set to a high level. |
1 |
CVDTXx pins defined in ITCTXA register are set to a low level. |
0 |
ITCTXA register is not used, the pins defined in ITCTXBA are controlled by TRIS and LAT registers. |
Bits 1:0 – PC0[1:0] CVDANx Pin Level Bits
| Value | Description |
|---|---|
3 |
CVDANx pins is tri-stated. |
2 |
CVDANx pins is set to a high level. |
1 |
CVDANx pins is set to a low level. |
0 |
CVDANx is not used, the pin is controlled by TRIS and LAT registers. |