17.2.1.21 Math Sequence Commands
Array Map Register
Legend: r = Reserved bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | SMATHMAP |
| Offset: | 0x7C3084 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | MATHSEQ3[2:0] | SECOND3 | ACC3 | CMP3 | SPLIT3[1:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | MATHSEQ2[2:0] | SECOND2 | ACC2 | CMP2 | SPLIT2[1:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | MATHSEQ1[2:0] | SECOND1 | ACC1 | CMP1 | SPLIT1[1:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | MATHSEQ0[2:0] | SECOND0 | ACC0 | CMP0 | SPLIT0[1:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:29 – MATHSEQ3[2:0] Math Sequence Number Bits for Commands from
SnMATHCMD12 to SnMATHCMD15
These bits must
match MATHSEQ[2:0] bits settings in the ITCSLxSEQ register.
Bit 28 – SECOND3 Second Math Sequence Bit for Commands from SnMATHCMD12 to
SnDATACMD15
This bit must be set if SECOND
bit is set in the acquisition SnDATACMDx command.
Bit 27 – ACC3 Accumulations Enable Bit for Commands from SnMATHCMD12 to
SnDATACMD15
This bit must be set if ACCCNT
[3:0] bits are not zero in the ITCSLxSEQ register.
Bit 26 – CMP3 Comparator Enable Bit for Commands from SnMATHCMD12 to
SnDATACMD15
This bit must be set if
CM[2:0] bits are not zero in the ITCLSxCON register.
Bits 25:24 – SPLIT3[1:0] Several Sequences
Split Bits for Commands from SnMATHCMD12 to SnMATHCMD15
Bits 23:21 – MATHSEQ2[2:0] Math Sequence Number Bits for Commands from SnMATHCMD8 to
SnMATHCMD11
These bits must match
MATHSEQ[2:0] bits settings in the ITCSLxSEQ register.
Bit 20 – SECOND2 Second Math Sequence Bit for Commands from SnMATHCMD8 to
SnDATACMD11
This bit must be set if SECOND
bit is set in the acquisition SnDATACMDx command.
Bit 19 – ACC2 Accumulations Enable Bit for Commands from SnMATHCMD8 to
SnDATACMD11
This bit must be set if ACCCNT
[3:0] bits are not zero in ITCSLxSEQ register.
Bit 18 – CMP2 Comparator Enable Bit for Commands from SnMATHCMD8 to
SnDATACMD11
This bit must be set if
CM[2:0] bits are not zero in the ITCLSxCON register.
Bits 17:16 – SPLIT2[1:0] Several Sequences
Split Bits for Commands from SnMATHCMD8 to SnMATHCMD11
Bits 15:13 – MATHSEQ1[2:0] Math Sequence Number Bits for Commands from SnMATHCMD4 to
SnMATHCMD7
These bits must match
MATHSEQ[2:0] bits settings in ITCSLxSEQ register.
Bit 12 – SECOND1 Second Math Sequence Bit for Commands from SnMATHCMD4 to
SnDATACMD7
This bit must be set if SECOND
bit is set in the acquisition SnDATACMDx command.
Bit 11 – ACC1 Accumulations Enable Bit for Commands from SnMATHCMD4 to
SnDATACMD7
This bit must be set if ACCCNT
[3:0] bits are not zero in the ITCSLxSEQ register.
Bit 10 – CMP1 Comparator Enable Bit for Commands from SnMATHCMD4 to
SnDATACMD7
This bit must be set if
CM[2:0] bits are not zero in the ITCLSxCON register.
Bits 9:8 – SPLIT1[1:0] Several Sequences
Split Bits for Commands from SnMATHCMD4 to SnMATHCMD7
Bits 7:5 – MATHSEQ0[2:0] Math Sequence Number Bits for Commands from SnMATHCMD0 to
SnMATHCMD3
These bits must match
MATHSEQ[2:0] bits settings in the ITCSLxSEQ register.
Bit 4 – SECOND0 Second Math Sequence Bit for Commands from SnMATHCMD0 to
SnDATACMD3
This bit must be set if SECOND
bit is set in the acquisition SnDATACMDx command.
Bit 3 – ACC0 Accumulations Enable Bit for Commands from SnMATHCMD0 to
SnDATACMD3
This bit must be set if ACCCNT
[3:0] bits are not zero in ITCSLxSEQ register.
Bit 2 – CMP0 Comparator Enable Bit for Commands from SnMATHCMD0 to
SnDATACMD3
This bit must be set if
CM[2:0] bits are not zero in the ITCLSxCON register.
Bits 1:0 – SPLIT0[1:0] Several Sequences
Split Bits for Commands from SnMATHCMD0 to SnMATHCMD3
