17.2.1.1 Control Register 1

Note:

Set the ADON bit only after the ITC module has been configured. Changing ITC configuration bits when ON = 1 will result in unpredictable behavior.

Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; S = Bit can be Set only; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown

Name:	ITCCON1
Offset:	0x380


Bit	31	30	29	28	27	26	25	24
	Reserved[1:0]						Reserved	Reserved
Access	R	R					R	R
Reset	0	0					1	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ON		SIDL	SLPEN	CVDEN			SIGN
Access	R/W		R/W	R/W	R/W			R/W
Reset	0		0	0	0			0


Bit	7	6	5	4	3	2	1	0

Access
Reset

Bits 31:30 – Reserved[1:0]

Bit 25 – Reserved

Bit 24 – Reserved

Bit 15 – ON ITC Enable bit⁽¹⁾

Value	Description
`1`	ITC module is enabled.
`0`	ITC module is off.

Bit 13 – SIDL Sleep in Idle Enable bit

Value	Description
`1`	ITC module goes to sleep in Idle mode.
`0`	ITC module is active in Idle mode.

Bit 12 – SLPEN Operation in Sleep Enable bit

Value	Description
`1`	The ITC works in Sleep mode.
`0`	The ITC in Sleep mode is disabled.

Bit 11 – CVDEN CVD Capacitance Array Enable bit

Value	Description
`1`	Additional to C_HOLD capacitance array is enabled.
`0`	Additional to C_HOLD capacitance array is disabled.

Bit 8 – SIGN Result Sign Format Selection bit

Value	Description
`1`	The ITCRESx result is in signed format.
`0`	The ITCRESx result is un-signed.