17.2.1.14 List x Post-Processing
Timers Delay Selection Register
Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; R =
Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0';
-n = Value at POR; '1' = Bit is set; '0' = Bit is
cleared; x = Bit value is unknown
Name:
ITCLSxTMR
Offset:
0x3B4, 0x3D0, 0x3EC
Bit
31
30
29
28
27
26
25
24
TMRD[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
TMRC[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TMRB[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TMRA[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 31:24 – TMRD[7:0] Post-Processing
Command Sequence Timer D Delay Selection Bits in TADs bits
Bits 23:16 – TMRC[7:0] Post-Processing
Command Sequence Timer C Delay Selection Bits in TADs bits
Bits 15:8 – TMRB[7:0] Post-Processing
Command Sequence Timer B Delay Selection Bits in TADs bits
Bits 7:0 – TMRA[7:0] Post-Processing
Command Sequence Timer A Delay Selection Bits in TADs bits
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