17.2.1.3 Status Register
Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; R =
Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0';
-n = Value at POR; '1' = Bit is set; '0' = Bit is
cleared; x = Bit value is unknown
| Name: | ITCSTAT |
| Offset: | 0x388 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TSTDATA[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TSTDATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSTEN | DRDY | ||||||||
| Access | R/W | R | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INT3 | INT2 | INT1 | INT0 | ||||||
| Access | HS | HS | HS | HS | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 31:16 – TSTDATA[15:0] Test Data Value bits
Bit 15 – TSTEN Test Mode Enable bit
| Value | Description |
|---|---|
1 |
The conversion result is replaced with TSTDATA[15:0] value. |
0 |
The Test mode is disabled. |
Bit 10 – DRDY ITC Ready bit
| Value | Description |
|---|---|
1 |
The ITC can be triggered. |
0 |
The ITC is not ready for operation. |
Bit 3 – INT3 List 3 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
List 3 generated the ITC interrupt. |
0 |
List 3 did not generate the ITC interrupt. |
Bit 2 – INT2 List 2 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
List 2 generated the ITC interrupt. |
0 |
List 2 did not generate the ITC interrupt. |
Bit 1 – INT1 List 1 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
List 1 generated the ITC interrupt. |
0 |
List 1 did not generate the ITC interrupt. |
Bit 0 – INT0 List 0 Interrupt Flag bit
| Value | Description |
|---|---|
1 |
List 0 generated the ITC interrupt. |
0 |
List 0 did not generate the ITC interrupt. |