17.2.1.2 Control Register 2

Legend: HC = Bit is Cleared by Hardware; HS = Bit is Set by Hardware; R = Readable Bit; W = Writable Bit; U = Unimplemented Bit, read as '0'; -n = Value at POR; '1' = Bit is set; '0' = Bit is cleared; x = Bit value is unknown

Name:	ITCCON2
Offset:	0x384


Bit	31	30	29	28	27	26	25	24
	TMRPR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	TMRPR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
					TRGEN3	TRGEN2	TRGEN1	TRGEN0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0

Access
Reset

Bits 31:16 – TMRPR[15:0] Internal Timer Period Selection bits

These bits select the internal timer period in the ITC clock cycles. This timer can be used to trigger the ITC.

Value	Description
`65535`	PERIOD = 65536 x ADC5 TADs
...
`1`	PERIOD = 2 x ADC5 TADs
`0`	PERIOD = ADC5 TADs

Bit 11 – TRGEN3 List 3 Enable bit

Value	Description
`1`	Triggers for List 3 are enabled.
`0`	Triggers for List 3 are disabled.

Bit 10 – TRGEN2 List 2 Enable bit

Value	Description
`1`	Triggers for List 2 are enabled.
`0`	Triggers for List 2 are disabled.

Bit 9 – TRGEN1 List 1 Enable bit

Value	Description
`1`	Triggers for List 1 are enabled.
`0`	Triggers for List 1 are disabled.

Bit 8 – TRGEN0 List 0 Enable bit

Value	Description
`1`	Triggers for List 0 are enabled.
`0`	Triggers for List 0 are disabled.