17.2.1.15 Records Pair Configuration Register
Legend: r = Reserved Bit; R = Readable Bit; W = Writable Bit; U =
Unimplemented Bit, read as '0'; -n = Value at POR;
'1' = Bit is set; '0' = Bit is cleared; x =
Bit value is unknown
| Name: | ITCRECx |
| Offset: | 0x3F0, 0x3F4, 0x3F8, 0x3FC, 0x400, 0x404, 0x408, 0x40C, 0x410, 0x414, 0x418, 0x41C, 0x420, 0x424, 0x428, 0x42C |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| GRDB(x+1)[1:0] | GRDA(x+1)[1:0] | ACCDONE(x+1) | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PIN(x+1)[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| GRDBx[1:0] | GRDAx[1:0] | ACCDONEx | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PINx[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 30:29 – GRDB(x+1)[1:0] CVD Guard B Assignment bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
Guard B is assigned to a pin specified by PIN[6:0] + 1. |
01 |
Guard B is assigned to a pin specified by PIN[6:0] - 1. |
00 |
Guard B is not used. |
Bits 28:27 – GRDA(x+1)[1:0] CVD Guard A Assignment bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
Guard A is assigned to a pin specified by PIN[6:0] + 1. |
01 |
Guard A is assigned to a pin specified by PIN[6:0] - 1. |
00 |
Guard A is not used. |
Bit 24 – ACCDONE(x+1) Accumulations Done Flag bit
| Value | Description |
|---|---|
1 |
The specified number of accumulations has been completed. This bit automatically set by hardware only after the sequence finishes execution and is automatically cleared by hardware when the ITCRESx register associated with the record is read. |
0 |
The specified number of accumulations is not finished. |
Bits 22:16 – PIN(x+1)[6:0] Analog Input Selection bits
| Value | Description |
|---|---|
127-32 |
Reserved |
31 |
CVDAN31 |
... |
|
1 |
CVDAN1 |
0 |
CVDAN0 |
Bits 14:13 – GRDBx[1:0] CVD Guard B Assignment bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
Guard B is assigned to a pin specified by PIN[6:0] + 1. |
01 |
Guard B is assigned to a pin specified by PIN[6:0] - 1. |
00 |
Guard B is not used. |
Bits 12:11 – GRDAx[1:0] CVD Guard A Assignment bits
| Value | Description |
|---|---|
11 |
Reserved |
10 |
Guard A is assigned to a pin specified by PIN[6:0] + 1. |
01 |
Guard A is assigned to a pin specified by PIN[6:0] - 1. |
00 |
Guard A is not used. |
Bit 8 – ACCDONEx Accumulations Done Flag bit
| Value | Description |
|---|---|
1 |
The specified number of accumulations has been completed. This bit automatically set by hardware only after the sequence finishes execution and is automatically cleared by hardware when the ITCRESx register associated with the record is read. |
0 |
The specified number of accumulations is not finished. |
Bits 6:0 – PINx[6:0] Analog Input Selection bits
| Value | Description |
|---|---|
127-32 |
Reserved |
31 |
CVDAN31 |
... |
|
1 |
CVDAN1 |
0 |
CVDAN0 |