3.3.16.1 X Address Generation Unit

The X AGU is used by all instructions and supports all addressing modes. The X AGU consists of a read AGU (X RAGU) and a write AGU (X WAGU), which operate independently on separate read and write buses during different phases of the instruction cycle. The X read data bus is the return data path for all instructions that view data space as a combined X and Y address space. It is also the X address space data path for the dual operand read instructions (DSP instruction class). The X write data bus is the only write path to the combined X and Y data space for all instructions.

The X AGU supports linear addressing through all of the address space. It can, therefore, generate EAs within the range 0x000000 to 0xFFFFFF.

The X RAGU starts its EA calculation during the prior instruction cycle, using information derived from the just prefetched instruction. The X RAGU EA is presented to the address bus at the beginning of the instruction cycle.

The X WAGU starts its EA calculation at the beginning of the instruction cycle. The EA is presented to the address bus during the write phase of the instruction.

Both the X RAGU and the X WAGU support Modulo Addressing.

Bit-Reversed Addressing is supported by the X WAGU only.