3.3.16.4 Data Alignment

The ISA supports long word (32-bit), word (16-bit) and byte (8-bit)-sized operations. Data are aligned in data memory and registers as long words, but all data space EAs resolve to bytes. Data word and byte reads will read the complete 32-bit word that contains the word or byte, using the LSbs of any EA to determine which word or byte to select within the CPU. The selected word or byte is placed onto the lsw or byte of the X data path (no byte accesses are possible from the Y data path as the MAC-class of instruction can only fetch words or long words). That is, data memory and registers are organized as four parallel byte-wide entities with a shared (long word) address decode but separate write lines. Data byte writes will only write to the corresponding side of the array or register which matches the byte address.

Note: Byte reads will always read the entire word, so mechanisms to clear or set peripheral status bits when read (e.g. quick flag clearing mechanisms) are not allowed.

As a consequence of this byte addressability, all EA calculations must be scaled to step through long word aligned memory. For example, the core must recognize that Post-Modified Register Indirect Addressing mode, [Ws]+=1, will result in a value of Ws+1 for byte operations, Ws+2 for word operations and Ws+4 for long word operations.

Misaligned word or long word accesses are not supported. For word accesses, the LSb of the EA must be 1’b0. For long word accesses, the least significant two bits of the EA must be 2’b00. Therefore, care must be taken when mixing operations of different data widths or translating from 16-bit code. Should a misaligned read or write be attempted, an address error trap will be forced. If the Fault occurs during a read access, the read will be allowed to complete. If the Fault occurs during a write access, the write will also be allowed to complete (inhibiting the write would have been possible but inconsistent with other situations where an errant write could not be inhibited). In both cases, the address error trap will be asserted. The next instruction (already prefetched and underway) will be executed while the exception is arbitrated and acknowledged. When this instruction completes, the trap will then be taken, allowing the system and/or user to examine the machine state subsequent to execution of the address Fault.

Note: Byte and word ALU operations can produce results in excess of a byte or a word. However, to maintain 16-bit backwards code compatibility, the ALU result destination write from all operations maintains the same width as that of the source operands (i.e., MSbs of the destination are not modified) and the SR is updated based only upon the state of the result data.

A sign extend (SE) instruction is provided to allow users to translate 8-bit to16-bit and 16-bit to 32-bit signed values. Alternatively, for unsigned data, users can clear the MS portion of any W register through executing a byte or word zero extend (ZE).

Note: Care must be taken when mixing byte and word-sized instructions/operands.

Although most instructions are capable of operating on long word, word or byte data sizes, it should be noted that the DSP and some other instructions operate on long word or word-sized data only.

Figure 3-18. Data Alignment