3.3.19.1 Read-After-Write Dependency Rules

If the W register is used as a write operation destination in the current instruction, and the W register being read in the prefetched instruction is the same, the following rules apply.

• If the destination write (current instruction) does not modify the contents of Wn, no stalls will occur.
• If the source read (prefetched instruction) does not calculate an EA using Wn, no stalls will occur.

During each instruction cycle, the dsPIC33A hardware automatically checks to see if a RAW data dependency is about to occur. If the conditions specified above are not satisfied, the CPU automatically adds a one-instruction cycle delay before executing the prefetched instruction. The instruction stall provides enough time for the destination W register write to occur before the next (prefetched) instruction that uses the written data. Table 3-9 provides a summary of read-after-write dependency.