3.3.19.2 Instruction Stall Cycles

An instruction stall is essentially a wait period instruction cycle added in front of the read phase of an instruction to allow the prior write to complete before the next read operation. For interrupt latency, the stall cycle is associated with the instruction following the instruction where it was detected (i.e., stall cycles always precede instruction execution cycles).

If a RAW data dependency is detected, the dsPIC33A CPU begins an instruction stall. During an instruction stall, the following events occur.

• The write operation in progress (for the previous instruction) is allowed to complete as normal.
• Data space is not addressed until after the instruction stall.
• PC increment is inhibited until after the instruction stall.
• Further instruction fetches are inhibited until after the instruction stall.