9.3.12.3 CHx_DMA_CTRL_REG Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| [10:9] | DMA_BRSTM | 0 | Burst Mode 00: Burst mode 0; bursts of unspecified length 01: Burst mode 1; INCR4 or unspecified length 10: Burst mode 2; INCR8, INCR4 or unspecified length 11: Burst mode 3; INCR16, INCR8, INCR4, or unspecified length |
| 8 | DMA_ERR | 0 | Bus error bit. Indicates that a bus error has been observed on the input AHB_HRESPM[1:0] coming from the AHB bus matrix, originating from the Cortex-M3 processor (or fabric master). This bit is cleared by the software. |
| [7:4] | DMAEP | 0 | The endpoint number (EP0/EP1/EP2/EP3/EP4) this channel is assigned to. |
| 3 | DMAIE | 0 | DMA interrupt enable |
| 2 | DMAMODE | 0 | Selects DMA Transfer mode. 0: DMA Mode 0 transfer 1: DMA Mode 1 transfer |
| 3 | DMA_DIR | 0 | Selects the DMA transfer direction. 0: DMA write (receive endpoint) 1: DMA read (transmit endpoint) |
| 2 | DMA_ENAB | 0 | Enables the DMA transfer and will cause the transfer to begin. |
Note:
- Allowed values of x are 1, 2, 3, and 4, corresponding to DMA channels 1 through 4.
- For CH2_DMA_CTRL_REG register the address is 0x40043214.
- For CH3_DMA_CTRL_REG register the address is 0x40043224
- For CH4_DMA_CTRL_REG register the address is 0x40043234.