9.3.12.5 CHx_DMA_COUNT_REG Bit Definitions

Table 9-107. CHx_DMA_COUNT_REG (0x4004320C)
Bit NumberNameReset ValueFunction
[31:0]DMA_COUNT0The DMA memory address for the corresponding DMA channel.

If DMA is enabled with a count of 0, the bus will not be requested and a DMA interrupt will be generated.

Notes:

  • Allowed values of x are 1, 2, 3, and 4, corresponding to DMA channels 1 through 4.
  • For CH2_DMA_COUNT_REG register the address is 0x4004321C.
  • For CH3_DMA_COUNT_REG register the address is 0x4004322C.
  • For CH4_DMA_COUNT_REG register the address is 0x4004323C.