9.3.12.1 DMA_REGISTER Description

Table 9-103. DMA_REGISTER Description
Register Name	Address Offset from 0x40043000	Width	R/W Type	Description
Table 9-104	0x0200	8	R	Provides an interrupt for each DMA channel. This interrupt register is cleared when read. When any bit of this register is set, the output DMA_NINT (output from DMA USB controller going to the Cortex-M3 processor) is asserted low. Bits in this register is set if the DMA Interrupt Enable bit for the corresponding channel is enabled (CHx_DMA_CNTL_REG.bit3).
CH1_DMA_CTRL_REG	0x0204	10	RW	Provides the DMA transfer control for channel 1. The enabling, transfer direction, transfer mode, and the DMA Burst modes are all controlled by this register.
CH1_DMA_ADDR_REG	0x0208	32	RW	Identifies the current memory address of the DMA channel 1. The initial memory address written to this register must have a value such that its modulo 4 value is equal to 0. That is, CH1_DMA_ADDR_ADDR[1:0] must be equal to 00. The lower two bits of this register are read only and cannot be set by the software. As the DMA transfer progresses, the memory address is incremented as bytes are transferred.
CH1_DMA_COUNT_REG	0x020C	32	RW	Identifies the current DMA count of the transfer for DMA channel 1. Software sets the initial count of the transfer, which identifies the entire transfer length. As the count progresses, this count is decremented as bytes are transferred.
CH2_DMA_CTRL_REG	0x0214	10	RW	Provides the DMA transfer control for channel 2. The enabling, transfer direction, transfer mode, and the DMA Burst modes are controlled by this register.
CH2_DMA_ADDR_REG	0x0218	32	RW	Identifies the current memory address of DMA channel 2. The initial memory address written to this register must have a value such that its modulo 4 value is equal to 0. That is, CH2_DMA_ADDR_ADDR[1:0] must be equal to 00. The lower two bits of this register are read only and cannot be set by the software. As the DMA transfer progresses, the memory address is incremented as bytes are transferred.
CH2_DMA_COUNT_REG	0x021C	32	RW	Identifies the current DMA count of the transfer for DMA channel 2. The software sets the initial count of the transfer, which identifies the entire transfer length. As the count progresses, this count is decremented as bytes are transferred.
CH3_DMA_CTRL_REG	0x0224	10	RW	Provides the DMA transfer control for channel 3. The enabling, transfer direction, transfer mode, and the DMA Burst modes are controlled by this register.
CH3_DMA_ADDR_REG	0x0228	32	RW	Identifies the current memory address of DMA channel 3. The initial memory address written to this register must have a value such that its modulo 4 value is equal to 0. That is, CH3_DMA_ADDR_ADDR[1:0] must be equal to 00. The lower two bits of this register are only read and cannot be set by the software. As the DMA transfer progresses, the memory address is incremented as bytes are transferred.
CH3_DMA_COUNT_REG	0x022C	32	RW	Identifies the current DMA count of the transfer for DMA channel 3. Software sets the initial count of the transfer, which identifies the entire transfer length. As the count progresses, this count is decremented as bytes are transferred.
CH4_DMA_CTRL_REG	0x0234	10	RW	This register provides the DMA transfer control for channel 4. The enabling, transfer direction, transfer mode, and the DMA burst modes are controlled by this register.
CH4_DMA_ADDR_REG	0x0238	32	RW	Identifies the current memory address of DMA channel 4. The initial memory address written to this register must have a value such that its modulo 4 value is equal to 0. That is, CH4_DMA_ADDR_ADDR[1:0] must be equal to 00. The lower two bits of this register are only read and cannot be set by the software. As the DMA transfer progresses, the memory address is incremented as bytes are transferred.
CH4_DMA_COUNT_REG	0x023C	32	RW	Identifies the current DMA count of the transfer for DMA channel 4. Software sets the initial count of the transfer, which identifies the entire transfer length. As the count progresses, this count is decremented as bytes are transferred.