9.3.14.1 Link Power Management Register Descriptions
| Register Name | Address Offset from 0x40043000 | Width | R/W Type | Reset Value | Description |
|---|---|---|---|---|---|
| Table 9-116 | 0x0360 | 16 | R | 0 | Defines the attributes of an LPM transaction and sleep cycle. In both Host mode and Peripheral mode, the meaning of this register is same; however, the source of the data is different for Host and Peripheral modes as follows: In Peripheral mode: The values in this register contains the equivalent attributes that were received in the last LPM transaction that was accepted. This register is updated with the LPM packet contents if the response to the LPM transaction was an ACK. This register can be updated through software. In all other cases, this register holds its current value. In Host mode: Software sets up the values in this register to define the next LPM transaction that is transmitted. These values are inserted in the payload of the next LPM transaction. |
| Table 9-117 | 0x0362 | 8 | R | 0 | Provides controls for LPM based on Peripheral mode and Host mode. |
| Table 9-119 | 0x0363 | 8 | R | 0 | Provides enable bits for the interrupts in LPM_INTR_REG. If a bit in this register is set to 1, MC_NINT will be asserted (low) when the corresponding interrupt in the LPM_INTR_REG is set. If a bit in this register is set to 0, the corresponding register in LPM_INTR_REG is still set but MC_NINT will not be asserted (low). On reset, all bits in this register are reset to 0. |
| Table 9-120 | 0x0364 | 7 | R | 0 | Provides status of the LPM power state. When a bit is set to 1, if the corresponding enable bit is also set to 1, the output MC_NINT is asserted (low). If the corresponding enable bit is set to 0, then the output MC_NINT is not asserted. On reset, all bits in this register are reset to 0. This register is clear on read. |
| Table 9-122 | 0x0365 | 7 | R | 0 | Holds the function address that is placed in the LPM payload. This has relevance in Host mode only. |