9.3.5.11 TEST_MODE_REG Bit Definitions

Table 9-20. TEST_MODE_REG (0x4004300F)
Bit Number Name Reset Value Function
7 Force_Host 0 The Arm® Cortex®-M3 processor (or fabric master) sets this bit to instruct the core to enter Host mode when the session bit is set, regardless of whether it is connected to any peripheral. The state of the CID input, HostDisconnect, and LineState signals is ignored. The core will then remain in Host mode until the session bit is cleared, even if a device is disconnected, and if the Force_Host bit remains set, will re-enter Host mode the next time the session bit is set. While in this mode, the status of the HOSTDISCON signal from the PHY may be read from bit 7 of the DevCtl register.
The operating speed is determined from the Force_HS and Force_FS bits, as shown in Table 9-21.
6 FIFO_Access 0 The Cortex-M3 processor (or fabric master) sets this bit to transfer the packet in the endpoint 0 TX FIFO to the endpoint 0 Rx FIFO. This bit is cleared automatically.
5 Force_FS 0 The Cortex-M3 processor (or fabric master) sets this bit either in conjunction with bit 7 above or to force the USB controller into Full speed mode when it receives a USB reset.
4 Force_HS 0 The Cortex-M3 processor (or fabric master) sets this bit either in conjunction with bit 7 above or to force the USB controller into High speed mode when it receives a USB reset.
3 Test_Packet 0 (High speed mode) The Cortex-M3 processor (or fabric master) sets this bit to enter Test_Packet test mode. In this mode, the USB controller repetitively transmits on the bus a 53-byte test packet, the form of which is defined in the USB specification revision 2.0, Section 7.1.20 (and in section 28.4).

The test packet has a fixed format and must be loaded into the endpoint 0 FIFO before the test mode is entered.
2 Test_K 0 (High speed mode) The Cortex-M3 processor (or fabric master) sets this bit to enter Test_K test mode. In this mode, the USB controller transmits a continuous K on the bus.
1 Test_J 0 (High speed mode) The Cortex-M3 processor (or fabric master) sets this bit to enter Test_J test mode. In this mode, the USB controller transmits a continuous J on the bus.
0 Test_SE0_NAK 0 (High speed mode) The Cortex-M3 processor (or fabric master) sets this bit to enter Test_SE0_NAK test mode. In this mode, the USB controller remains in high-speed mode but responds to any valid IN token with a NAK.