13.4.3.7 SPI SCLK Generation Register (CLK_GEN)

The following table describes the clock modes used to calculate the SPICLK divider. Table 13-16 describes the SPICLK rates in different modes.

Table 13-15. CLK_GEN
Bit NumberNameR/WReset ValueDescription
[31:8]ReservedR/W0Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation.
[7:0]CLK_GENR/W0Specifies the methodology used to calculate the SPICLK divider.

CLK_MODE = 0:

SPICLK = 1 / (2 CLK_GEN + 1) where CLK_GEN = 0 to 15

CLK_MODE = 1:

SPICLK = 1 / (2 × (CLK_GEN + 1)) where CLK_GEN = 0 to 255

The following table lists the SPICLK rates in different modes.

Table 13-16. CLK_MODE Example, APB Clock = 153.8 MHz
CLK_MODE=0CLK_MODE=1
SPICLK = 1 / (2CLKRATE + 1)

where CLKRATE = 0 to 15

SPICLK = 1 / (2 × (CLKRATE + 1))

where CLKRATE = 0 to 255

CLKRATESPI ClockCLKRATESPI Clock
076,900,000076,900,000
138,450,000138,450,000
219,225,000225,633,333.33
39,612,500319,225,000
44,806,250415,380,000
52,403,125512,816,666.67
61,201,562.5610,985,714.29
7600,781.2579,612,500
8300,390.62588,544,444.444
9150,195.31297,690,000
1075,097.656106,990,909.091
1137,548.828116,408,333.333
1218,774.414125,915,384.615
139,387.207135,492,857.143
144,693.603145,126,666.667
152,346.801154,806,250
……
255300,390.625