13.4.3.4 SPI Interrupt Clear Register (INT_CLEAR)
The following table describes the Interrupt Clear register. A read to this register has no effect. It returns all zeroes.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:6] | Reserved | W | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 5 | SSEND | W | Write one to clear the interrupt | |
| 4 | CMDINT | W | Write one to clear the interrupt | |
| 3 | TXCHUNDRUN | W | 0 | Transmit channel under-run |
| 2 | RXCHOVRFLW | W | 0 | Receive channel over flow |
| 1 | RXRDYCLR | W | 0 | Clears receive ready (RX_RDY) |
| 0 | TXDONECLR | W | 0 | Clears transmit done (TX_DONE) |