13.4.3.14 SPI Command Size Register
The following table describes the Command size register.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:8] | Reserved | R/W | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| [7:0] | CMDSIZE | R/W | 0 | Number of frames after SPI_SS[0] going active that the CMD interrupt should be generated. This controls the RxCMD interrupt. The internal counters count frames from SPI_SS[0] going low. It automatically resets and starts counting again once SSEL goes inactive. In TI mode, back- to-back frames are counted, any gaps in data causes the counter to start counting again. |