13.4.3.9 SPI Masked Interrupt Status Register
The following table describes the Masked Interrupt Status (MIS) register. It is a read-only register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:6] | Reserved | R/W | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 5 | SSEND | R | Indicates that SPI_X_SS[x] has gone inactive. When this is high, the interrupt is active. | |
| 4 | CMDINT | R | Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames (SPI_X_SS[x] held active). When this is high, the interrupt is active. | |
| 3 | TXCHUNDDMSKINT | R | 0 | Masked interrupt status. Reading this returns
interrupt status. Masked interrupt status = Raw interrupt status and interrupt mask (Table 13-9 register) MIS = RIS and Table 13-9[7:4] Masked status of transmit channel under-run TXCHUNDMSKINT=TXCHUNDRINT and INTTXUNRRUN |
| 2 | RXCHOVRFMSKINT | R | 0 | Masked status of receive channel overflow. RXCHOVRFMSKINT = RXCHOVRFINT and INTRXOVRFLO |
| 1 | RXRDYMSKINT | R | 0 | Masked status of receive data ready (data received in FIFO). RXRDYMSKINT = RXRDY and INTTXDATA |
| 0 | TXDONEMSKINT | R | 0 | Masked status of transmit done (data shifted out) TXDONEMSKINT = TXDONE and INTRXDATA |