13.4.3.15 SPI Hardware Status Register
The following table describes the Hardware Status register. This register allows the Cortex-M3 processor to control the hardware Status register used in the slave protocol controller.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| [31:4] | Not used | R/W | 0 | These bits are undefined. The value that the slave transmits depends on the data that is queued in the transmit FIFO. |
| [3:2] | USER | R/W | 0 | These bits are set by the CPU. Their function is undefined but could be used to send additional status or request information to the master. |
| 1 | TXBUSY | R/W | 0 | 0: Master may request the requested data.
There are PKTSIZE frames of data in the transmit FIFO (when AUTOPOLL is set to
PKTSIZE - 1) 1: Indicates not ready to transmit data. |
| 0 | RXBUSY | R/W | 0 | 1: Indicates that the receive buffer is busy (not empty). 0: Indicates that up to PKTSIZE frames of command followed by data may be sent to the slave. |