4.2.5.5.2 Consecutive Reads Incrementing through Memory

In this case, four reads from addresses 0x60000010, 0x60000014, 0x60000018, and 0x6000001C are initiated by the AHB master in succession. The first word is returned 9 clock cycles later (as shown in the preceding figure), but the second word occurs in the following cycle, 9 clock cycles later the third word is provided and the fourth word occurs in the next clock cycle. This pattern is repeated as the memory is incremented as shown in the following figure.

Figure 4-6. Timing Diagram Showing Consecutive Reads Incrementing through Memory

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