7.4.1.9.1 Notes on the Destination Address Register (DAR)

Address is word aligned at the start.
Address increments on each successful transfer at the destination end.
HPDMA controller starts reading the data from source memory and transfers to destination memory.
Software can write all 32-bit destination addresses to prevent non-word aligned transfers at the start and 2 LSBs, 1:0, are masked in the hardware.
The destination address will be updated in the same field when the descriptor transfer is in progress.

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