15.3.14 Clock Monitor Control Register

Table 15-19. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	CMxCON
Offset:	0x3200, 0x3230, 0x3260, 0x3290


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ON		SIDL	SLPEN
Access	R/W		R/W	R/W
Reset	1		0	0


Bit	7	6	5	4	3	2	1	0
			CNTDIV[1:0]		FLTINJ[1:0]			WIDTH
Access			R/W	R/W	R/W	R/W		R/W
Reset			0	0	0	0		0

Bit 15 – ON Clock Monitor Enable bit

Value	Description
1	Clock Monitor is enabled
0	Clock Monitor is disabled

Bit 13 – SIDL Stop in Idle bit

Value	Description
1	Clock Monitor block will stop when IDLE mode is entered
0	Clock Monitor block will continue to operate when IDLE mode is entered

Bit 12 – SLPEN Sleep Mode Enable bit

Value	Description
1	Module continues to operate in Sleep modes
0	Module does not operate in Sleep modes

Bits 5:4 – CNTDIV[1:0] Counter Divider Selection bits⁽¹⁾

These selection bits allow dividing down the input clock to the counter. The function is intended to detect over-clocking in Clock Monitor mode of operation.

Value	Description
11	Reserved
10	Divide-by 4
01	Divide-by 2
00	Divide-by 1

Bits 3:2 – FLTINJ[1:0] Fault Injection Enable Control bits⁽²⁾

These control bits allow injecting an artificially faulty condition into the macro for the purpose of inoperation reliability self-testing.

Value	Description
11	Artificial catastrophic Fault injected into the macro by blanking the monitored clock
10	High-frequency drift Fault injected into the macro by halving the reference clock
01	Low-frequency drift Fault injected into the macro by halving the monitored clock
00	No artificial Fault injected

Bit 0 – WIDTH Time Window Selection Control bit^(3,4)

This control bit selects whether the Time Window Generator’s clock high pulse defines the accumulation time window period.

Value	Description
1	Rising edge to next falling edge
0	Rising edge to rising edge, see WINPR[31:0]