15.3.10 PLL Divider Register

Table 15-15. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PLLxDIV
Offset:	0x3184, 0x3190


Bit	31	30	29	28	27	26	25	24
					PLLPRE[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	1


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	PLLFBDIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	0	0	1	0	0	0


Bit	7	6	5	4	3	2	1	0
			POSTDIV1[2:0]			POSTDIV2[2:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			1	1	1	0	0	1

Bits 27:24 – PLLPRE[3:0] PLLx Reference Clock Prescale bits

Value	Description
1111	16x divide
1110	15x divide
...
0010	2x divide
0001	1x divide
0000	undefined, not allowed

Bits 15:8 – PLLFBDIV[7:0] PLLx Feedback Divider bit

Value	Description
11111111	256x divide
11111110	255x divide
...
00000010	2x divide
00000001	1x divide
00000000	undefined, not allowed

Bits 5:3 – POSTDIV1[2:0] PLLx Post Divider #1 bit

Value	Description
111	7x divide
110	6x divide
...
010	2x divide
001	1x divide
000	undefined, not allowed

Bits 2:0 – POSTDIV2[2:0] PLLx Post Divider #2 bit

Value	Description
111	7x divide
110	6x divide
...
010	2x divide
001	1x divide
000	undefined, not allowed

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.