15.3.15 Clock Monitor Control Register

Note:
  1. Do not change the value while in operation.
  2. CMxHWT/CMxLWT and CMxHFT/CMxLFT must all be cleared before the Fault can be injected.
  3. When set high, the function is intended for the pulse width measurement feature where the monitored clock (as opposed to the reference clock) is expected to clock the time window generator responsible for defining the measurement time period. Conversely, the reference clock is used to clock the counter at a higher rate of switching frequency.
  4. When set high, the content of WINPR[31:0] prescaler is ignored while both the time window generator and the counter are reset.
Table 15-20. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: CMxSTAT
Offset: 0x3204, 0x3234, 0x3264, 0x3294

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     HWTLWTHFTLFT 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
      TRIGSATDBUFV 
Access R/WR/WR/W 
Reset 000 

Bit 11 – HWT High Warning Threshold Status bit

This status bit is set by hardware when the captured count value exceeds that of the high warning threshold register content. In other words, the monitored clock is at a higher frequency than desired (or the reference clock is running slower than expected).
ValueDescription
1High threshold warning
0No warning

Bit 10 – LWT Low Warning Threshold Status bit

This status bit is set by hardware when the captured count value is less than that of the low warning threshold register content. In other words, the monitored clock is at a lower frequency than desired (or the reference clock is running faster than expected).
ValueDescription
1Low threshold warning
0No warning

Bit 9 – HFT High Failing Threshold Status bit

This status bit is set by hardware when the captured count value exceeds that of the high failing threshold register content. In other words, the monitored clock is at a higher frequency than allowed (or the reference clock is running slower than allowed). When instanced as a Fail Safe Clock Monitor, a hardware switchover to the backup clock source will occur.
ValueDescription
1High threshold failing
0No failure

Bit 8 – LFT Low Failing Threshold Status bit

This status bit is set by hardware when the captured count value is less than that of the low failing threshold register content. In other words, the monitored clock is at a lower frequency than allowed (or the reference clock is running faster than allowed). When instanced as a Fail-Safe Clock Monitor, a hardware switchover to the backup clock source will occur.
ValueDescription
1Low threshold failing
0No failure

Bit 2 – TRIG Time Window Generator Trigger Status bit

This status bit indicates the start of the accumulation time window. When set high by hardware, the condition implies that the selected reference clock is toggling properly. Clock Monitor Saturation Interrupt is invoked.
ValueDescription
1The accumulation time window has (re)started/stopped
0The accumulation time window has not started

Bit 1 – SATD Counter Saturated Status bit

This status bit indicates the counter has saturated without being captured.
ValueDescription
1The counter has saturated at SAT[31:0]
0The counter has not saturated

Bit 0 – BUFV Buffer Valid Status bit

This status bit indicates successful count capturing into the Data Buffer register. Reset to 1’b0, this bit is set high by hardware when the current count value of the counter is captured into BUF[31:0] at the end of each accumulation time window. As a result, the Count Ready Interrupt (upbs_event[4]) is invoked.

ValueDescription
1Accumulated count has been captured into BUF[31:0] and is ready for software use
0Accumulated count has not been captured into BUF[31:0] yet, or has been obsoleted by catastrophic failure of the monitored clock for more than one accumulation window