15.3.11 PLL VCO Divider Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | VCOxDIV |
| Offset: | 0x3188, 0x3194 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| INTDIV[14:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| INTDIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 30:16 – INTDIV[14:0] PLL VCO Integer Divider bit
Number of Source Clocks in each 1/2 period of the Divided Clock.
Period Ex:
Divided Clock Period = [Source Clock Period] * INT * 2
Frequency Ex:
111111111111111 = Clock Generator
Divided Clock = Source Clock divided by 65,534
(32,767 *2)
| Value | Description |
|---|---|
| 000000000000011 | Clock Generator Divided Clock = Source Clock divided by 6 (3*2) |
| 000000000000010 | Clock Generator Divided Clock = Source Clock divided by 4 (2*2) |
| 000000000000001 | Clock Generator Divided Clock = Source Clock divided by 2 (1*2) |
| 000000000000000 | Clock Generator Divided Clock = Source Clock (no divider) |