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15.3.16 Clock Monitor Prescaler
Register
Table 15-21. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: CMxWINPR Offset: 0x3208, 0x3238,
0x3268, 0x3298
Bit 31 30 29 28 27 26 25 24 WINPR[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset
Bit 23 22 21 20 19 18 17 16 WINPR[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset
Bit 15 14 13 12 11 10 9 8 WINPR[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset
Bit 7 6 5 4 3 2 1 0 WINPR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset
Bits 31:0 – WINPR[31:0] Clock Monitor
Prescaler Prescaler value to
alter ratio of reference and monitored clocks.
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