15.3.18 Clock Monitor Buffer Register

Table 15-23. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	CMxBUF
Offset:	0x3210, 0x3240, 0x3270, 0x32A0


Bit	31	30	29	28	27	26	25	24
	BUF[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	23	22	21	20	19	18	17	16
	BUF[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	15	14	13	12	11	10	9	8
	BUF[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	7	6	5	4	3	2	1	0
	BUF[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset

Bits 31:0 – BUF[31:0] Monitored Clock Count Value.

The Clock Monitor Data Buffer register contains the final accumulated count recorded by the counter during the previous accumulation window. Its content feeds the threshold limit comparators.