15.3.23 Clock Monitor Low Threshold Warning Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CMxLWARN |
| Offset: | 0x3224, 0x3254, 0x3284, 0x32B4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LWARN[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LWARN[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LWARN[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LWARN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
Bits 31:0 – LWARN[31:0] Clock Monitor Low Threshold Warning bits
The Clock Monitor Low Threshold Warning register contains the lower warning threshold limit against which the captured count is compared (see LWT).
Warning is signaled when CMxBUF[31:0] < CMxLWARN, so this register defines the slowest monitored frequency, fastest scaled reference frequency or shortest reference pulse width that can be measured before triggering a warning. Setting CMxLWARN = 0x00000000 will have the effect of disabling this threshold.