15.3.2 Oscillator Configuration Register

Table 15-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	OSCCFG
Offset:	0x3104


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
							FRCLPWR[1:0]
Access							R/W	R/W
Reset							0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
			POSCIOFNC	KICK	GAIN[1:0]		POSCMD[1:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	1	1

Bits 17:16 – FRCLPWR[1:0] FRC Low-Power Mode Enable bits

Value	Description
11	Reserved
10	Reserved
01	FRC Low-Power mode
00	FRC Standard-Power mode

Bit 5 – POSCIOFNC Primary CLKO Enable Configuration bit

Value	Description
1	CLKO output signal active on the OSCO pin; POSC must be disabled or configured for the External Clock mode
0	CLKO output disabled

Bit 4 – KICK Kick-Starter Programmability for Primary Oscillator bit

Value	Description
1	Boost the kick start
0	Default kick start

Bits 3:2 – GAIN[1:0] Current Gain Programmability for Oscillator (Output Drive) bits

G3>G2>G1>G0

Value	Description
11	Gain is G3 (use for 24-32 MHz crystals)
10	Gain is G2 (use for 16-24 MHz crystals)
01	Gain is G1 (use for 8-16 MHz crystals)
00	Gain is G0 (use for 4-8 MHz crystals)

Bits 1:0 – POSCMD[1:0] Primary Oscillator Selection bit

Value	Description
11	OFF (use pin as GPIO)
10	HS Oscillator mode selected (10 MHz-32 MHz)
01	MS Oscillator mode selected (3.5 MHz-10 MHz)
00	External clock

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