15.3.22 Clock Monitor High Threshold Warning Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CMxHWARN |
| Offset: | 0x3220, 0x3250, 0x3280, 0x32B0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| HWARN[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| HWARN[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HWARN[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HWARN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
Bits 31:0 – HWARN[31:0] Clock Monitor High Threshold Warning bits
The Clock Monitor High Threshold Warning register contains the upper warning threshold limit against which the captured count is compared (see HFT).
Warning is signaled when CMxBUF[31:0] > CMxHWARN, so this register defines the fastest monitored frequency, slowest scaled reference frequency or longest reference pulse width that can be measured before triggering a warning. Setting CMxHWARN = 0xFFFFFFFF will have the effect of disabling this threshold.