15.3.20 Clock Monitor High Threshold Failing Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | CMxHFAIL |
| Offset: | 0x3218, 0x3248, 0x3278, 0x32A8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| HFAIL[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| HFAIL[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HFAIL[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HFAIL[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | |||||||||
Bits 31:0 – HFAIL[31:0] Clock Monitor High Threshold Failing bits
The Clock Monitor High Threshold Failing register contains the upper failing threshold limit against which the captured count is compared, see HWT. Failure is signaled when CMxBUF[31:0] > CMxHFAIL, so this register defines the fastest monitored frequency, slowest scaled reference frequency, or longest reference pulse width that can be measured before triggering a failure. Setting CMxHFAIL = 0xFFFFFFFF will have the effect of disabling this threshold.