15.3.21 Clock Monitor Low Threshold Failing Register

Table 15-26. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	CMxLFAIL
Offset:	0x321C, 0x324C, 0x327C, 0x32AC


Bit	31	30	29	28	27	26	25	24
	LFAIL[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	23	22	21	20	19	18	17	16
	LFAIL[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	15	14	13	12	11	10	9	8
	LFAIL[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset


Bit	7	6	5	4	3	2	1	0
	LFAIL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset

Bits 31:0 – LFAIL[31:0] Clock Monitor Low Threshold Failing bits

The Clock Monitor Low Threshold Failing register contains the lower failing threshold limit against which the captured count is compared (see LFT). Failure is signaled when CMxBUF[31:0] < CMxLFAIL, so this register defines the slowest monitored frequency, fastest scaled reference frequency or shortest reference pulse width that can be measured before triggering a failure. Setting CMxLFAIL = 0x00000000 will have the effect of disabling this threshold.

Value	Description
1
0